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1 lt1002 dual, matched precision operational amplifier strain gauge signal conditioner with bridge excitation + lt1001 3 10 4 11 13 6 2.0k* 8.2k lm329 +15v 2 3 6 1002 ta01 2k 4.99k* 2k 15v *rn60c film resistors +15v in4148 350 w bridge 2n2219 reference out to monitoring a/d converter in4148 100 w 5w 100 w 5w 10k zero 1 m f 340k* 0 to 10v out * 301k 1.1k* 2n2907 + 1 / 2 lt1002 + 1 / 2 lt1002 gain trim input offset voltage match ( m v) 100 number of units 70 60 50 40 30 20 10 0 ?0 0 40 1002 ta02 ?0 80 100 ?0 40 20 60 v s = 15v t a = 25 c 287 units tested distribution of offset voltage match features applicatio n s u n thermocouple amplifiers n strain gauge amplifiers n low level signal processing n medical instrumentation n precision dual limit threshold detection n instrumentation amplifiers n guaranteed low offset voltage lt1002a 60 m v max lt1002 100 m v max n guaranteed offset voltage match lt1002a 40 m v max lt1002 80 m v max n guaranteed low drift lt1002a 0.9 m v/ c max lt1002 1.3 m v/ c max n guaranteed cmrr lt1002a 110db min lt1002 110db min n guaranteed channel separation lt1002a 132db min lt1002 130db min n guaranteed maching characteristics n low noise 0.35 m v p-p descriptio n u the lt ? 1002 dual, matched precision operational amplifiers combine excellent individual amplifier performance with tight matching and temperature tracking between amplifiers. in the design, processing, and testing of the device, particular attention has been paid to the optimization of the entire distribution of several key parameters and their matching. consequently, the specifications of even the low cost commer- cial grade (the lt1002c) have been spectacularly improved compared to presently available devices. essentially, the input offset voltage of all units is less than 80 m v, and matching between amplifiers is consistently beter than 60 m v (see distribution plot below). input bias and offset currents, channel separation, common mode and power suply rejections of the lt1002c are all specified at levels which were previsouly attainable only on very expensive, selected grades of other dual devices. power dissipation is nearly halved compared to the most popular precision duals, without ad- versely affecting noise or speed performance. a by-product of lower dissipation is decreased warm-up drift. for even better performance in a single precision op amp, refer to the lt1001 data sheet. a bridge signal conditioning application is shown below. this circuit illustrates the requirement for both excel- lent matching and individual amplifier specifications. , ltc and lt are registered trademarks of linear technology corporation.
2 lt1002 lt1002am/lt1002ac LT1002M/lt1002c symbol parameter conditions min typ max min typ max units v os input offset voltage note 1 20 60 25 100 m v d v os long term input offset voltage d time stability notes 2 and 3 0.3 1.5 0.4 2.0 m v/month i os input offset current 0.3 2.8 0.4 4.2 na i b input bias current 0.6 3.0 0.7 4.5 na e n input noise voltage 0.1hz to 10hz (note 2) 0.35 0.7 0.38 0.75 m v p-p e n input noise voltage density f o = 10hz (note 5) 10.3 20.0 10.5 20.0 f o = 1000hz (note 2) 9.6 11.5 9.8 12.0 nv ? hz a vol large signal voltage gain r l 3 2k w , v o = 12v 400 800 350 800 v/mv r l 3 1k w , v o = 10v 250 500 220 500 cmrr common mode rejection ratio v cm = 13v 110 126 110 126 db psrr power supply rejection ratio v s = 3v to 18v 108 123 105 123 db r in input resistance differential mode note 4 20 100 13 80 m w input voltage range 13 14 13 14 v v out maximum output voltage swing r l 3 2k w 13 14 13 14 v r l 3 1k w 12 13.5 12 13.5 sr slew rate r l 3 2k w (note 4) 0.1 0.25 0.1 0.25 v/ m s gbw gain bandwidth product note 4 0.4 0.8 0.4 0.8 mhz p d power dissipation no load 46 75 48 85 mw per amplifier no load, v s = 3v 4 7 4 8 absolute m axi m u m ratings w ww u supply voltage (note 6)......................................... 22v differential input voltage ...................................... 30v input voltage equal to supply voltage output short circuit duration ......................... indefinite operating temperature range lt1002am/LT1002M ....................... C 55 c to 125 c lt1002ac/lt1002c ............................... 0 c to 70 c storage temperature range all grades ......................................... C 65 c to 150 c lead temperature (soldering, 10 sec.)................. 300 c package/order i n for m atio n w u u 1 2 3 4 5 6 7 top view j package 14 pin hermetic n package 14 pin plastic 14 13 12 11 10 9 8 null (a) null (a) in (a) +in (a) v (b) out (b) v+ (b) v+ (a) out (a) v?(a) +in (b) in (b) null (b) null (b) + + a b lt1002amj LT1002Mj lt1002acj lt1002cj lt1002acn lt1002cn offset voltage max at 25 c order part no. 60 m v 100 m v 60 m v 100 m v 60 m v 100 m v note: device may be operated even if insertion is reversed; this is due to inherent symmetry of pin locations of amplifiers a and b. (note 6) electrical characteristics, i dividual a plifiers uw v s = 15v, t a = 25 c, unless otherwise noted
3 lt1002 electrical characteristics, i dividual a plifiers uw v s = 15v, C 55 c t a 125 c, unless otherwise noted lt1002am LT1002M symbol parameter conditions min typ max min typ max units v os input offset voltage note 1 l 30 150 45 230 m v d v os average input offset voltage drift l 0.2 0.9 0.3 1.3 m v/ c d temp i os input offset current l 0.8 5.6 1.2 8.5 na i b input bias current l 1.0 6.0 1.5 9.0 na a vol large signal voltage gain r l 3 2k w , v o = 10v l 300 700 200 700 v/mv cmrr common mode rejection ratio v cm = 13v l 106 122 104 120 db psrr power supply rejection ratio v s = 3v to 18v l 102 117 96 117 db input voltage range l 13 14 13 14 v v out output voltage swing r l 3 2k w l 12.5 13.5 12.0 13.5 v p d power dissipation no load l 55 90 60 100 mw per amplifier lt1002ac lt1002c symbol parameter conditions min typ max min typ max units v os input offset voltage note 1 l 20 100 30 160 m v d v os average input offset voltage drift l 0.2 0.9 0.3 1.3 m v/ c d temp i os input offset current l 0.5 4.2 0.6 5.7 na i b input bias current l 0.7 4.5 1.0 6.0 na a vol large signal voltage gain r l 3 2k w , v o = 10v l 350 750 250 750 v/mv cmrr common mode rejection ratio v cm = 13v l 108 124 106 123 db psrr power supply rejection ratio v s = 3v to 18v l 105 120 100 120 db input voltage range l 13 14 13 14 v v out output voltage swing r l 3 2k w l 12.5 13.8 12.5 13.8 v p d power dissipation no load l 50 85 55 90 mw per amplifier v s = 15v, 0 c t a 70 c, unless otherwise noted the l denotes the specifications which apply over the full operating temperature range. for mil-std components, please refer to ltc 883c data sheet for test listing and parameters. note 1: offset voltage measured with high speed test equipment, approximately 1second after power is applied. note 2: this parameter is tested on a sample basis only. note 3: long term input offset voltage stability refers to the averaged trend line of v os versus time over extended periods after the first 30 days of operation. excluding the initial hour of operation, changes in v os during the first 30 operating days are typically 2.5 m v. note 4: parameter is guaranteed by design. note 5: 10hz noise voltage density is sample tested on every lot. devices 100% tested at 10hz are available on request. note 6: the v + supply terminals are completely independent and may be powered by separate supplies if desired (this approach, however, would sacrifice the advantages of the power supply rejection ratio matching). the v C supply terminals are both connected to the common substrate and must be tied to the same voltage. both v C pins should be used.
4 lt1002 at v s = 15v, t a = 25 c, unless otherwise noted lt1002am/ac LT1002M/c symbol parameter conditions min typ max min typ max units input offset voltage match C 15 40 C 25 80 m v i b + average non-inverting bias current C 0.6 3.5 C 0.7 4.8 na i os + non-inverting offset current C 0.6 3.5 C 0.7 6.0 na i os C inverting offset current C 0.6 3.5 C 0.7 6.0 na d cmrr common mode rejection ratio match v cm = 13v 110 132 C 108 132 C db d psrr power supply rejection ratio match v s = 3v to 18v 108 130 C 102 128 C db channel seperation f 10hz (note 4) 132 148 C 130 146 C db atchi g characteristics u w at v s = 15v, C 55 c t a 125 c, unless otherwise noted lt1002am LT1002M symbol parameter conditions min typ max min typ max units input offset voltage match l C 50 140 C 60 230 m v input offset voltage tracking l C 0.3 1.0 C 0.4 1.5 m v/ c i b + average non-inverting bias current l C 1.5 6.0 C 1.8 10.0 na i os + non-inverting offset current l C 1.5 6.5 C 1.8 12.0 na i os C inverting offset current l C 1.5 6.5 C 1.8 12.0 na d cmrr common mode rejection ratio match v cm = 13v l 106 126 102 124 C db d psrr power supply rejection ratio match v s = 3v to 18v l 102 122 94 120 C db atchi g characteristics u w at v s = 15v, 0 c t a 70 c, unless otherwise noted lt1002ac lt1002c symbol parameter conditions min typ max min typ max units input offset voltage match l C 30 85 C 45 150 m v input offset voltage tracking l C 0.3 1.0 C 0.4 1.5 m v/ c i b + average non-inverting bias current l C 1.0 4.5 C 1.2 7.0 na i os + non-inverting offset current l C 1.0 5.0 C 1.2 8.5 na i os C inverting offset current l C 1.0 5.0 C 1.2 8.5 na d cmrr common mode rejection ratio match v cm = 13v l 108 130 C 105 128 C db d psrr power supply rejection ratio match v s = 3v to 18v l 105 126 C 98 124 C db atchi g characteristics u w
5 lt1002 typical perfor m a n ce characteristics u w distribution of offset voltage match drift with temperature input offset voltage drift with temperature ( m v/ c) number of units 70 60 50 40 30 20 10 0 1002 g02 1.2 0.8 0.4 0 +0.4 +0.8 +1.2 260 units tested v s = 15v offset voltage drift with temperature of six representative units offset voltage tracking with temperature of six representative units long term stability of four representative units time (months) 0 offset voltage change ( m v) 4 1001 g07 1 2 3 5 10 5 0 ? ?0 frequency (hz) 1 1 3 10 30 100 0.1 1 3 10 10 100 1000 1002 g09 voltage noise nv/ hz t a = 25 c v s = 3 to 18v voltage current 1/f corner 70hz 1/f corner 4hz 0.3 current noise pa/ hz time (seconds) 0 noise voltage 100nv/div 8 1001 g08 2 4 6 10 distribution of offset voltage drift with temperature (individual amplifiers) distribution of offset voltage of individual amplifiers offset voltage match drift with temperature ( m v/ c) number of units 35 30 25 20 15 10 5 1002 g03 1.2 0.8 0.4 0 +0.4 +0.8 +1.2 130 units tested v s = 15v warm-up drift time after power on ? both amplifiers (minutes) 0 change in offset voltage (microvolts) 5 4 3 2 1 0 4 1002 g06 1 2 3 5 v s = 15v t a = 25 c n14 plastic packge j14 hermetic dip packge temperature ( c) ?0 offset voltage match ( m v) 100 80 60 40 20 0 20 40 60 80 100 0 50 75 1002 g04 ?5 25 100 125 lt1002am lt1002am lt1002am LT1002M LT1002M v s = 15v LT1002M temperature ( c) ?0 individual amplifier offset voltage ( m v) 100 80 60 40 20 0 20 40 60 80 100 0 50 75 1002 g04 ?5 25 100 125 lt1002am lt1002am lt1002am LT1002M LT1002M LT1002M 0.1hz to 10hz noise noise spectrum input offset voltage ( m v) 100 80 number of units 100 80 60 40 20 0 60 1002 g01 ?0 40 ?0 0 20 40 80 100 574 units tested v s = 15v t a = 25 c
6 lt1002 typical perfor m a n ce characteristics u w differential input (volts) 0.1 0 inverting or non-inverting input bias current (ma) 10 20 30 1.0 3.0 0.3 10 30 1002 g12 v s = 15v t a = 25 c i b ? 1 na input bias current vs. differential input voltage temperature ( c) ?0 1200k 1000k 800k 600k 400k 200k 0 25 75 1002 g13 ?5 0 50 100 125 open loop voltage gain (v/v) v s = 15v, v o = 12v v s = 3v, v o = 1v matching and individual amplifier bias and offset currents vs temperature temperature ( c) ?0 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 25 75 1001 g10 ?5 0 50 100 125 input bias and offset currents (na) v s = 15v matching: non inverting bias current m a t c h i n g : i n v e r i n g & n o n - i n v . o f f s e t c u r r e n t i n d i v i d u a l a m p b i a s c u r r e n t i n d i v i d u a l a m p o f f s e t c u r r e n t common-mode input voltage ?5 input bias current (na) 1.5 1.0 0.5 0 ?5 1.0 1.5 ?0 ? 0 5 1002 g11 10 15 v s = 15v t a = 25 c device with positive input current device with negative input current + v cm i b common-mode input resistance = = 280g w 28v 0.1na input bias current over the common mode range open loop voltage gain vs temperature frequency (hz) 0.1 open loop voltage gain (db) 10m 1002 g14 10 100 10k 1m 1 1k 100k 140 120 100 80 60 40 20 0 ?0 t a = 25 c v s = 15v v s = 3v open loop voltage gain frequency response frequency (mhz) 0.1 0.2 0.5 voltage gain (db) phase shift (degrees) 1 1002 g15 phase margin 55 c = 63 125 c = 57 20 16 12 8 4 0 ? ? 80 100 120 140 160 180 200 220 2 phase 25 c gain 125 c v s = 15v gain 25 c & 55 c 25 c phase margin = 60 gain, phase shift vs. frequency open loop gain mismatch vs frequency frequency (hz) 1 open loop gain mismatch (percent) 1.0 0.8 0.6 0.4 0.2 0 10k 1002 g16 10 100 1k 100k v s = 15v t a = 25 c percent gain mismatch = output a ?output b 1 / 2 (output a + output b) 100% frequency (hz) 1 output impedance ( w ) 100 10 1 0.1 0.01 0.001 10k 1002 g17 10 100 1k 100k a v = 1000 a v = +1 i o = 1ma v s = 15v t a = 25 c closed loop output impedance power supply rejection and psrr match vs frequency frequency (hz) power supply rejection (db) 160 140 120 100 80 60 40 20 0 1002 g18 0.1 1 10 100 1k 10k 100k v s = 15v 2v pp t a = 25 c match (negative supply) match (positive supply) positive supply negative supply
7 lt1002 small signal transient response typical perfor m a n ce characteristics u w frequency (hz) 100 channel separation (db) 160 150 140 130 120 110 100 90 80 1k 10k 1002 g19 100k 1m v s = 15v t a = 25 c r s =10 w r s =100 w r s =1k common mode rejection and cmrr match vs frequency channel separation vs frequency frequency (hz) common mode rejection (db) 160 140 120 100 80 60 40 20 0 1002 g20 1 10 100 1k 10k 100k 1m v s = 15v t a = 25 c cmrr match ( cmrr) < common mode limit vs temperature temperature ( c) ?0 v + 0.2 0.4 0.6 0.8 1.0 +1.0 +.8 +.6 +.4 +.2 v 25 75 1002 g21 ?5 0 50 100 125 common mode limit (volts) referred to power supply v = 1.2 to 4v v = 12 to 18v v + = 12 to 18v v + = 1.2 to 4v supply voltage (v) supply current (ma) 2.0 1.5 1.0 0.5 9 15 1002 g22 3 6 12 18 21 ?5 c 125 c 25 c supply churrent vs. supply voltage for each amplifier large signal transient response 1002 g23 frequency (khz) 1 output voltage, peak-to-peak (volts) 28 24 20 16 12 8 4 0 10 100 1000 1002 g24 v s = 15v t a = +25 c maximum undistorted output vs. frequency a v = +1, c l = 1000pf 1002 g27 small signal transient response capacitive load (picofarads) 100 percent overshoot 1002 g26 1000 10,000 100,000 100 80 60 40 20 0 v s = 15v t a = 25 c v in = 100mv r l > 50k voltage follower overshoot vs capacitive load a v = +1, c l = 50pf 1002 g25
8 lt1002 typical perfor m a n ce characteristics u w load resistance ( w ) 100 300 output swing (volts) 16 12 8 4 0 1000 3k 10k 1002 g28 v s = 15v t a = 25 c positive swing negative swing time from output short (minutes) 0 short circuit current (ma) sinking sourcing 2 50 40 30 20 10 10 20 30 40 ?0 1002 g29 134 ?5 c ?5 c 25 c 25 c 125 c 125 c v s = 15v output short circuit current vs time output swing vs. load resistance applicatio n s i n for m atio n wu u u the lt1002 dual amplifier may be inserted directly into op-10, op207, op227 sockets with or without removal of external nulling potentiometers. offset voltage adjustment the input offset voltage of the lt1002, and its drift with temperature, are permanently trimmed at wafer testing to a low level. however, if further adjustment of v os is necessary, nulling with a 10k or 20k potentiometer will not degrade drift with temperature. trimming to a value other than zero creates a drift of (v os / 300) m v/ c, e.g. if v os is adjusted to 300 m v, the change in drift will be 1 m v/ c. the adjustment range with a 10k or 20k pot is approximately 2.5mv. if less adjustment range is needed, the sensitivity and resolution of the nulling can be improved by using a smaller pot in conjunc- tion with fixed resistors. the example has an approximate null range of 100 m v. in matching applications, both amplifiers can be trimmed to zero, or the offset of one amplifier can be trimmed to match the offset of the other. offset adjustment, however, slightly degrades the gain, common-mode and power- supply rejection match between the two op amps. fortu- nately, the guaranteed offset voltage match of the lt1002 is very low, in most applications offset adjustment will be unnecessary. improved sensitivity adjustment standard adjustment + 15v 1 / 2 lt1002 +15v 3 (10) (11) 4 (9) (8) 13 (6) 14 (7) output input 1002 ta03 12 (5) 2 10k or 20k 1 + 15v 1 / 2 lt1002 +15v 3 (10) (11) 4 (9) (8) 13 (6) 14 output input 1002 ta04 12 (5) 2 1k 7.5k 7.5k 1 (7)
9 lt1002 applicatio n s i n for m atio n wu u u test circuit for offset voltage and its drift with temperature + 15v +15v *50k * 100 w * 50k 3 (10) (11) 4 14 (7) 13 (6) v o 1002 ta05 v o = 1000 v os * resistors must have low thermoelectric potential. 12 (5) 1 / 2 lt1002 0.1hz to 10hz noise test circuit the device under test should be warmed up for three minutes and shielded from air currents. turn the device 180 to measure the noise of side b. + + 100k w 2k w 100k 4.3k 110k scope 1 r in = 1m w 0.1 m f 4.7 m f 24.3k 10 w 1002 ta06 0.1 m f 22 m f voltage gain = 50,000 2.2 m f device under test 1 / 2 lt1002 a 1 / 2 lt1002 b (peak to peak noise measured in 10 sec interval) this circuit is also used as burn-in configuration for the lt1002, with supply voltages increased to 20v. unless proper care is exercised, thermocouple effects, caused by temperature gradients across dissimilar metals at the contacts to the input terminals, can exceed the inherent drift of the amplifier. air currents should be minimized, package leads should be short, the two input leads should be as close together as possible and main- tained at the same temperature. channel separation this parameter is defined as the ratio of the change in input offset voltage of one amplifier to the change in output voltage of the other amplifier causing the offset change. at low frequencies the lt1002s channel separation is an almost unmeasurable 148db. as frequency increases, pin to pin capacitance of the package, between the output of one amplifier and the inputs of the other, becomes domi- nant. since these pins are non-adjacent, the capacitance is only 0.02pf. to maintain the lt1002s excellent channel separation at higher frequencies, the socket and pc board capacitances should be minimized. power supplies the lt1002 is specified over a wide range of power supply voltages from 3v to 18v. operation with lower supplies is possible, down to 1.2v (two ni-cad batteries). how- ever, with 1.2v supplies, the device is stable only in closed loop gains of + 2 or higher (or inverting gain of one or higher). the v+ supply terminals are completely independent and may be powered by separate supplies if desired (this approach, however, would sacrifice the advantages of the power supply rejection ratio matching). the vC supply terminals are both connected to the common substrate and must be tied to the same voltage. both v C pins should be used.
10 lt1002 applicatio n s i n for m atio n wu u u advantages of matched dual op amps in many applica- tions the performance of a system depends on the match- ing between two operational amplifiers rather than the individual characteristics of the two op amps. two or three op amp instrumentation amplifiers, tracking voltage refer- ences and low drift active filters are some of the circuits requiring matching between two op amps. the well-known triple op amp configuration illustrates these concepts. output offset is a function of the differ- ence between the offsets of the two halves of the lt1002. this error cancellation principle holds for a considerable number of input referred parameters in addition to offset voltage and its drift with temperature. input bias current will be the average of the two non-inverting input currents (i b + ). the difference between these two currents (i os + ) is the offset current of the instrumentation amplifier. the difference between the inverting input currents (i os C ) will cause errors flowing through r1, r2, and r3. common- mode and power supply rejections will be dependent only on the match between the two amplifiers (assuming perfect resistor matching). the concepts of common mode and power supply rejec- tion ratio match ( d cmrr and d psrr) are best demon- strated with a numerical example: assume cmrr a = + 1.0 m v/v or 120db, and cmrr b = + 0.75 m v/v or 122.5db, then d cmrr = 0.25 m v/v or 132db; if cmrr b = C 0.75 m v/v which is still 122.5db, then d cmrr = 1.75 m v/v or 115db. clearly, the lt1002, by specifying and guaranteeing all of these matching parameters, can significantly improve the performance of matching dependent circuits. 1002 ta07 r1 10k 1% r4 100 w 1% r6 10k 1% r5 100 w 1% input output + gain = 1000 + a 1 / 2 lt1002 + b 1 / 2 lt1002 lt1037 input + r2 10k 1% r7 r9 9.76k 1% r3 r8 2.1k 1% c1 100pf r10 100k 200 w 200 w three op amp instrumentation amplifier trim r8 for gain trim r9 for dc common mode rejection trim r10 for ac common mode rejection typical performance of the instrumentation amplifier: input offset voltage = 25 m v input bias current = 0.7na input resistance = 200 g w input offset current = 0.6na input noise = 0.5 m v p-p power bandwidth (v 0 = 10v) = 80khz
11 lt1002 applicatio n s i n for m atio n wu u u precision 10v reference 3 lm129a 4 10 11 13 14 0.1% 1k 12 6 7 5 1002 ta08 10k 1% 3.3k 0.1% 10k + out 2 10.000v 15v +15v out 1 10.000v 1 / 2 lt1002 + 1 / 2 lt1002 130k 5% 8.2k 1% 1% 3.3k when the upper or lower limit is exceeded the led lights up. positive feedback to one of the nulling terminals creates 5 to 20 m v of hysteresis on both amplifiers. this feedback changes the offset voltage of the lt1002 by less than 5 m v. therefore, the basic accuracy of the comparator is limited only by the low offset voltage of the lt1002. dual limit microvolt comparator 4 10 3 11 13 12 5 1 14 6 8 7 upper limit input lower limit 1002 ta09 430k 1% 20k 5% 15v 15v +15v flv117 39.2 w 1% 15k 1% 39.2 w 1% 15k 1% 1k 5% + + 1 / 2 lt1002 1 / 4 ca3118 1 / 4 ca3118 1 / 2 lt1002 1 / 4 ca3118 1 / 4 ca3118 430k 1% the lt1002 contributes less than 5% of the total drift with temperature, noise and long term drift of the reference. the accuracy of the C10v output is limited by the matching of the two 10k resistors.
12 lt1002 two op amp instrumentation amplifier + 1002 ta10 r3 10k 100k* r1 10k r2 100k r4 + output * trim for common-mode rejection + trim for gain gain = 1 + + + ? 100 inputs 1 / 2 lt1002 + 1 / 2 lt1002 2.2k+ r5 r4 r3 r2 + r3 r5 r3 r4 r2 r1 1 2 () precision amplifier drives 500 w load to 10v this application utilizes the guaranteed 10ma load driving capability of the lt1002. the offset voltage of amplifier a is the offset of the configuration. amplifier b provides the additional 10ma load current. when load resistor r l is removed, amplifier a sinks this current without affecting accuracy. in the gain of 1000 configuration shown, ap- proximately 0.3% gain accuracy can be realized. +15 15v +15v 15v 1002 ta11 100k input output 110k 1.1r f + 0.1r s 100 w 100 w r s 0.2r l r f 500 w r l 100 w r s + b 1 / 2 lt1002 + a 1 / 2 lt1002 applicatio n s i n for m atio n wu u u
13 lt1002 dead zone generator 1002 ta13 10k 0.1% 10k 0.1% 10k 0.1% 10k 0.1% 10k 0.1% input 10 to 10v output 0 to 10v 3 4 13 + 10 11 6 + in4148 in4148 1 / 2 lt1002 1 / 2 lt1002 precision absolute value circuit + + 2 3 1 8 6 + 2 3 6 1k 2n4393 q1 2n4393 q6 1002 ta12 ** 100k ** 100k 10k* 10k* 10k** 10k** 10k 2k 100k input 100k 4.7k 4.7k 10k 4.7k 3.3k 15pf 30pf +15v in914 15v lm301a 3 4 13 10 11 6 v out lm301a 15pf in914 * 1% film ** ratio match 0.05% q2, 3, 4, 5 ca 3096 transistor array 47pf q4 q2 v set dead zone control input 0 to 5v bipolar symmetry is excellent because one device, q2, sets both limits + q5 v set v set v out v in q3 1 / 2 lt1002 1 / 2 lt1002 applicatio n s i n for m atio n wu u u
14 lt1002 dual precision power supply (1) 0 to 10v in 100 m v steps (2) 0 to 100v in 1mv steps + + + +15v 15v +15 25k lm399 kvd 00000 ? 99999 + 1 kelvin-varley divider esi#dp311 + 3 100 w 13 in914 2n2219 2k 22k* 43k* (select) +15 100 w 5w 8.2k 4 10 4 0.1 2.2 22 m f 2n6533 2n2907 1002 ta14 +15 1.8k +15v 5k 90k* 10k* (select) trim?00v 100 w 15 w diodes = semtech # ff-15 output 2 0-100v, 25ma output 1 0-10v 25ma 6 in914 2k in914 11 + + 2 6 vn-46 triad ty-90 vn-46 33k 33k 74c74 33k 680pf kvd = esi#dp311 * = julie rsch. labs #r-44 3 lt301a d clk q q clamp set 1 / 2 lt1002 1 / 2 lt1002 applicatio n s i n for m atio n wu u u
15 lt1002 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. in 500 500 v v+ + q7 q5 q3 q6 q27 q28 q29 q24 q25 q31 q32 q4 q8 q11 q12 q33 q34 1002 ss q22 2k 2k q15 q26 20 240 120 180 w 20 3k 8k 1.5k 25k q16 q21 q23 q13 q14 55pf 20pf 3k 30pf q1b q10 q9 q19 q20 t1 q17 q18 q30 q2b q2a in null null 40k 40k 6k 6k out q1a 1 / 2 lt1002 package descriptio n u sche atic diagra w w dimensions in inches (millimeters) unless otherwise noted. t jmax q ja lt1002acn 125 c 100 c/w lt1002cn t jmax q ja lt1002acj 125 c 100 c/w lt1002cj lt1002amj 125 c 100 c/w LT1002Mj n14 0695 0.015 (0.380) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.045 ?0.065 (1.143 ?1.651) 0.065 (1.651) typ 0.018 0.003 (0.457 0.076) 0.100 0.010 (2.540 0.254) 0.005 (0.125) min 0.255 0.015* (6.477 0.381) 0.770* (19.558) max 3 1 2 4 5 6 7 8 9 10 11 12 13 14 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.025 0.015 +0.635 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) j14 0694 0.045 ?0.068 (1.143 ?1.727) 0.100 0.010 (2.540 0.254) 0.014 ?0.026 (0.360 ?0.660) 0.200 (5.080) max 0.015 ?0.060 (0.381 ?1.524) 0.125 (3.175) min 0.300 bsc (0.762 bsc) 0.008 ?0.018 (0.203 ?0.457) 0 ?15 0.385 0.025 (9.779 0.635) 1 234 56 7 0.220 ?0.310 (5.588 ?7.874) 0.785 (19.939) max 0.005 (0.127) min 14 11 8 9 10 13 12 0.025 (0.635) rad typ note: lead dimensions apply to solder dip or tin plate leads. 0.045 ?0.068 (1.143 ?1.727) full lead option 0.023 ?0.045 (0.584 ?1.143) half lead option corner leads option (4 plcs) n package 14-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) j package 14-lead cerdip (narrow 0.300, hermetic) (ltc dwg # 05-08-1110)
16 lt1002 lt/gp 0396 2k rev a ? printed in usa ? linear technology corporation 1985 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977

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